1. Field of the Invention
The invention relates to a delay locked loop, and more particularly to a delay locked loop with a common counter.
2. Description of the Related Art
The delay locked loop (DLL) is commonly utilized in computer environments for generating a required clock. If the needed clock rate increases, the low-skew clock distributions become important. The related computer environments include processors communicating with various kinds of memory devices and input/output devices. Taking the synchronous dynamic random access memory device (SDRAM) as an example, the data transfer rate is almost equal to that of the processors. In a DDR memory application, data is output from a DDR SDRAM to a memory controller at both rising and falling edges of a clock cycle. The DLL in the memory controller is designed to generate a delayed clock according to a memory clock for delaying the timing of input clock. In other words, the DLL provides a delay quantity to shift the rising or falling edges and the memory controller can store correct data in the latch device.
Please refer to FIG. 1. FIG. 1 is a block diagram of a related delay locked loop (DLL). The DLL 100 includes a multiplexer (MUX) 102, a frequency divider 104, an inverter 105, a phase detector 106, a counter 108, and a delay component 110. For example, a delay clock whose frequency is equal to 500 MHz is chosen and the DLL 100 needs to lock the delay clock to lag 90 degrees behind an input clock. A detailed description of locking the delay clock is provided in the following.
Assume that the MUX 102 chooses the clock CLK1 as the input clock IN whose frequency is equal to 1 GHz. The inverter 105 inverts the input clock IN to generate the reference clock REFCLK. The delay component 110 includes a plurality of delay chains. Different delay chains correspond to different operational bands of the input clock. In other words, the delay component 110 is a broadband delay component. The delay component 110 provides a predetermined delay quantity dt to the input clock CLK1 to output the delay clock FBCLK. The selecting signal SEL is utilized to select one delay chain. In this case, the length of the selecting signal SEL[1:0] is two bits and the selecting signal SEL[1:0] can select one of four different delay chains corresponding to different frequencies of the input clock. The phase detector 106 compares the phases of the delay clock FBCLK and the reference clock REFCLK. If the phase of the reference clock REFCLK leads, the up signal UP is triggered once. The counter 108 receives the up signal UP and adds the count value DCNT[7:0] by one when catching an edge (rising or falling) of the frequency-divided clock CNTCLK4. The frequency-divided clock CNTCLK4 is output from the frequency divider 104 and the period of the frequency-divided clock CNTCLK4 is four times greater than that of the input clock CLK1 since the frequency of the frequency-divided clock CNTCLK4 is divided by four. Please note that the dividing value is not limited to the value four, the dividing value can be eight or sixteen for example. The counter 108 continues counting to control the delay component 110 to increase the delay quantity dt until the phase of the delay clock lags 180 degrees behind the phase of the input clock. Once the phase of the delay clock lags by 180 degrees, the related DLL 100 is locked and the frequency of the input clock is changed from 1 GHz to 500 MHz. After changing the input clock to 500 MHz, the delay clock lags 90 degrees behind the input clock (the frequency is 500 MHz). In other words, each time the related DLL 100 generates the delay clock, the operating frequency of the input clock will be increased by two (e.g. from 500 MHz to 1 GHz) in the beginning, and recovered again (e.g. from 1 GHz to 500 MHz) when the DLL 100 is locked. This is not only time consuming but also difficult particularly when the operating frequency of the input clock is high. Additionally, the broadband delay component and the counter may not operate normally when the operating frequency of the input clock is high. In other words, the common counter may operate abnormally in some high bands.